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| ? semiconductor components industries, llc, 2012 may, 2012 ? rev. 0 1 publication order number: ncv7381/d ncv7381 flexray bus driver ncv7381 is a single ? channel flexray bus driver compliant with the flexray electrical physical layer specification rev. 3.0.1, capable of communicating at speeds of up to 10 mbit/s. it provides differential transmit and receive capability between a wired flexray communication medium on one side and a protocol controller and a host on the other side. ncv7381 mode control functionality is optimized for nodes permanently connected to car battery. it offers excellent emc and esd performance. key features general ? compliant with flexray electrical physical layer specification rev 3.0.1 ? flexray transmitter and receiver in normal ? power modes for communication up to 10 mbit/s ? support of 60 ns bit time ? flexray low ? power mode receiver for remote wakeup detection ? excellent electromagnetic susceptibility (ems) level over full frequency range. very low electromagnetic emissions (eme) ? bus pins protected against >10 kv system esd pulses ? safe behavior under missing supply or no supply conditions ? interface pins for a protocol controller and a host (txd, rxd, txen, rxen, stbn, bge, en, errn) ? inh output for control of external regulators ? local wakeup pin wake ? txen time ? out ? bge feedback ? supply pins v bat , v cc , v io with independent voltage ramp up: ? v bat supply parametrical range from 5.5 v to 50 v ? v cc supply parametrical range from 4.75 v to 5.25 v ? v io supply parametrical range from 2.3 v to 5.25 v ? compatible with 14 v and 28 v systems ? operating ambi ent temperature ? 40 c to +125 c (t amb_class1 ) ? junction temperature monitoring with two levels ? ssop ? 16 package flexray functional classes ? bus driver voltage regulator control ? bus driver ? bus guardian interface ? bus driver logic level adaptation ? bus driver remote wakeup quality ? automotive qualification according to aec ? q100 (rev. f) http://onsemi.com (top view) 1 v cc bp bm inh v io en txd pin connections see detailed ordering and shipping information in the package dimensions section on page 23 of this data sheet. ordering information ssop ? 16 dp suffix case 565ae gnd wake v bat errn rxen rxd txen bge stbn marking diagram nv7381 ? 0 awlyyww 1 16 a = assembly location wl = wafer lot yyww = year / work week = pb ? free package
ncv7381 http://onsemi.com 2 txd txen bge stbn rxd gnd bm control logic (normal mode / low ? power mode) receiver ncv7381 errn bus error detection wakeup detection voltage monitoring thermal shutdown host module bge module cc module inh rxen en wake bp control logic transmitter figure 1. block diagram v bat v cc v io v bat table 1. pin description pin number pin name pin type pin function 1 inh high ? voltage analog output external regulator control output 2 en digital input mode control input; internal pull ? down resistor 3 v io supply supply voltage for digital pins level adaptation 4 txd digital input data to be transmitted; internal pull ? down resistor 5 txen digital input transmitter enable input; when high transmitter disabled; internal pull ? up resistor 6 rxd digital output receive data output 7 bge digital input bus guardian enable input; when low transmitter disabled; internal pull ? down resistor 8 stbn digital input mode control input; internal pull ? down resistor 9 rxen digital output bus activity detection output; when low bus activity detected 10 errn digital output error diagnosis and status output 11 v bat supply battery supply voltage 12 wake high ? voltage analog input local wake up input; internal pull up or pull down (depends on voltage at pin wake) 13 gnd ground ground connection 14 bm high ? voltage analog input/output bus line minus 15 bp high ? voltage analog input/output bus line plus 16 v cc supply bus driver core supply voltage; 5 v nominal ncv7381 http://onsemi.com 3 application information ncv7381 bp bm gnd wake errn rxen inh en txd txen rxd bge stbn vbat bp bm wake gnd vio reg. cmc out out in inh flexray communication controller bus guardian host interface mcu in inh ecu vcc reg. figure 2. application diagram c vio c vcc c vbat v io v cc v bat r wake2 r wake1 c bus r bus1 r bus2 table 2. recommended external components for the application diagram component function min typ max unit c vbat decoupling capacitor on battery line, ceramic 100 nf c vcc decoupling capacitor on v cc supply line, ceramic 100 nf c vio decoupling capacitor on v io supply line, ceramic 100 nf r wake1 pull ? up resistor on wake pin 33 k r wake2 serial protection resistor on wake pin 3.3 k r bus1 bus termination resistor (note 1) 47.5 r bus2 bus termination resistor (note 1) 47.5 c bus common ? mode stabilizing capacitor, ceramic (note 2) 4.7 nf cmc common ? mode choke 100 h 1. tolerance 1%, type 0805 2. tolerance 20%, type 0805 ncv7381 http://onsemi.com 4 functional description operating modes ncv7381 can switch between several operating modes depicted in figure 3. in normal and receive ? only modes, the chip interconnects a flexray communication controller with the bus medium for full ? speed communication. these two modes are also referred to as normal ? power modes. in standby and sleep modes, the communication is suspended and the power consumption is substantially reduced. a wakeup on the bus or through a locally monitored signal on pin w ake can be detected and signaled to the host. go ? to ? sleep mode is a temporary mode ensuring correct transition between any mode and the sleep mode. all three modes ? standby, sleep and go ? to ? sleep ? are referred to as low ? power modes. the operating mode selected is a function of the host signals stbn and en, the state of the supply voltages and the wakeup detection. as long as all three supplies (v bat , v cc , v io ) remain above their respective under ? voltage detection levels, the logical control by en and stbn pins shown in figure 3 applies. influence of the power ? supplies and of the wakeup detection on the operating modes is described in subsequent paragraphs. normal mode transmitter: on receiver: on inh: high power cons.: normal standby mode receive ? only mode transmitter: off receiver: on inh: high power cons.: normal go ? to ? sleep mode transmitter: off receiver: wakeup ? detection inh: high power cons.: low sleep mode transmitter: off receiver: wakeup ? detection inh: floating power cons.: low stbn=h en=h stbn=h en=l stbn=l en=l stbn=l en=h stbn=l en=l stbn=l en=h stbn=h en=l stbn=h en=h stbn=l, en=h for ncv7381 http://onsemi.com 5 receive ? only mode stbn en errn error flag wake flag normal mode error flag standby mode go ? to ? sleep mode sleep mode normal mode dbdmodechange dbdmodechange dbdmodechange dbdmodechange dgo ? to ? sleep error flag wake flag figure 4. timing diagram of operating modes control by the stbn and en pins power supplies and power supply monitoring ncv7381 is supplied by three pins. v bat is the main supply both for ncv7381 and the full electronic module. v bat will be typically connected to the automobile battery through a reverse ? polarity protection. v cc is a 5 v low ? voltage supply primarily powering the flexray bus driver core in a normal ? power mode. v io supply serves to adapt the logical levels of ncv7381 to the host and/or the flexray communication controller digital signal levels. all supplies should be properly decoupled by filtering capacitors ? see figure 2 and table 2. all three supplies are monitored by under ? voltage detectors with individual thresholds and filtering times both for under ? voltage detection and recovery ? see table 18. logic level adaptation level shift input v io is used to apply a reference voltage uv dig = uv io to all digital inputs and outputs in order to adapt the logical levels of ncv7381 to the host and/or the flexray communication controller digital signal levels ncv7381 http://onsemi.com 6 internal flags the ncv7381 control logic uses a number of internal flags (i.e. one ? bit memories) reflecting important conditions or events. table 3 summarizes the individual flags and the conditions that lead to a set or reset of the flags. table 3. internal flags flag set condition reset condition comment local wakeup low level detected on wake pin in a low ? power mode low ? power mode is entered remote wakeup remote wakeup detected on the bus in a low ? power mode low ? power mode is entered wakeup local wakeup flag changes to set or remote wakeup flag changes to set normal mode is entered or low ? power mode is entered or any under ? voltage flag becomes set power ? on internal power supply of the chip becomes sufficient for the operation of the control logic normal mode is entered thermal warning junction temperature is higher than tjw (typ. 140 c) in a normal ? power mode and v bat is not in under ? voltage (junction temperature is below tjw in a normal ? power mode or the status register is read in a low ? power mode) and v bat is not in under ? voltage the thermal warning flag has no influence on the bus driver function thermal shutdown junction temperature is higher than tjsd (typ. 165 c) in a normal ? power mode and v bat is not in under ? voltage junction temperature is below tjsd in a normal ? power mode and falling edge on txen and v bat is not in under ? voltage the transmitter is disabled as long as the thermal shut- down flag is set txen timeout txen is low for longer than dbdtxact- ivemax (typ. 1.5 ms) and bus driver is in normal mode txen is high or normal mode is left the transmitter is disabled as long as the timeout flag is set bus error transmitter is enabled and data on bus are different from txd signal (sampled after each txd edge) (transmitter is enabled and data on bus are identical to txd signal) or transmitter is disabled the bus error flag has no influence on the bus driver func- tion v bat under ? voltage v bat is below the under ? voltage threshold for longer than dbduvv bat v bat is above the under ? voltage threshold for longer than dbdrv bat or wake flag becomes set v cc under ? voltage v cc is below the under ? voltage threshold for longer than dbduvv cc v cc is above the under ? voltage threshold for longer than dbdrv cc or wake flag becomes set v io under ? voltage v io is below the under ? voltage threshold for longer than duv io v io is above the under ? voltage threshold for longer than dbdrv io or wake flag becomes set error any of the following status bits is set: ? bus error ? thermal warning ? thermal shutdown ? txen timeout ? v bat under ? voltage ? v cc under ? voltage ? v io under ? voltage all of the following status bits are reset: ? bus error ? thermal warning ? thermal shutdown ? txen timeout ? v bat under ? voltage ? v cc under ? voltage ? v io under ? voltage ncv7381 http://onsemi.com 7 operating mode changes caused by internal flags changes of some internal flags described in table 3 can force an operating mode transition complementing or overruling the operating mode control by the digital inputs stbn and en which is shown in figure 3: ? setting the v bat or v io under ? voltage flag causes a transition to the sleep mode ? setting the v cc under ? voltage flag, while the bus driver is not in sleep, causes a transition to the standby mode ? reset of the under ? voltage flag (i.e. recovery from under ? voltage) re ? enables the control of the chip by digital inputs stbn and en. ? setting of the wake flag causes the reset of all under ? voltage flags and the ncv7381 transitions to the standby mode. the reset of the under ? voltage flags allows the external power supplies to stabilize properly if, for example, they were previously switched off during sleep mode. flexray bus driver ncv7381 contains a fully ? featured flexray bus driver compliant with electrical physical layer specification rev. 3.0.1. the transmitter part translates logical signals on digital inputs txen, bge and txd into appropriate bus levels on pins bp and bm. a transmission cannot be started with data_1. in case the transmitter is enabled for longer than dbdtxactivemax , the txen timeout flag is set and the current transmission is disabled. the receiver part monitors bus pins bp and bm and signals the detected levels on digital outputs rxd and rxen. the dif ferent bus levels are defined in figure 5. the function of the bus driver and the related digital pins in different operating modes is detailed in table 4 and table 5. ? the transmitter can only be enabled if the activation of the transmitter is initiated in normal mode. ? the receiver function is enabled by entering a normal ? power mode. bp bm idle_lp idle data_0 data_1 figure 5. flexray bus signals v cc /2 ubus table 4. transmitter function and transmitter ? related pins operating mode bge txen txd transmitted bus signal standby, go ? to ? sleep, sleep x x x idle_lp receive ? only x x x idle normal 0 x x idle 1 1 x idle 1 0 0 data_0 1 0 1 data_1 table 5. receiver function and receiver ? related pins operating mode signal on bus wake flag rxd rxen standby, go ? to ? sleep, sleep x not set high high x set low low normal, receive ? only idle x high high data_0 x low low data_1 x high low ncv7381 http://onsemi.com 8 bus guardian interface the interface consists of the bge digital input signal allowing a bus guardian unit to disable the transmitter and of the rxen digital output signal used to signal whether the communication signal is idle or not. bus driver voltage regulator control ncv7381 provides a high ? voltage output pin inh which can be used to control an external voltage regulator (see figure 2). the pin inh is driven by a switch to v bat supply. in normal, receive ? only, standby and go ? to ? sleep modes, the switch is activated thus forcing a high level on pin inh. in the sleep mode, the switch is open and inh pin remains floating. if a regulator is directly controlled by inh, it is then active in all operating modes with the exception of the sleep mode. bus driver remote wakeup detection during a low ? power mode and under the presence of v bat voltage, a low ? power receiver constantly monitors the activity on bus pins bp and bm. a valid remote wake ? up is detected when either a wakeup pattern or a dedicated wakeup frame is received. a valid remote wake ? up is also detected when wake ? up pattern has been started in normal ? power mode already. a wakeup pattern is composed of two data_0 symbols separated by data_1 or idle symbols. the basic wakeup pattern composed of data_0 and idle symbols is shown in figure 6; the wakeup pattern composed of data_0 and data_1 symbols ? referred to as ?alternative wakeup pattern? ? is depicted in figure 7. idle(_lp) data_0 idle(_lp) data_0 idle(_lp) 0 figure 6. valid remote wakeup pattern detected remote wakeup ubus udata0_lp ncv7381 http://onsemi.com 9 errn pin and status register provided v io supply is present together with either v bat or v cc , the digital output errn indicates the state of the internal ?error? flag when in normal mode and the state of the internal ?wake? flag when in standby, go ? to ? sleep or sleep. in receive ? only mode errn indicates either the state of the internal ?error? or the wakeup source (see table 6). the polarity of the indication is reversed ? errn pin is pulled low when the ?error? flag is set. the signaling on pin errn functions in all operating modes. table 6. signaling on errn pin stbn en conditions error flag wake flag errn high high ? not set x high set x low high low en has been set to high after previous wakeup not set x high set x low en has not been set to high after previous wakeup x set local high x set remote low low x ? x not set high x set low additionally, a full set of internal bits referred to as status register can be read through errn pin with en pin used as a clock signal ? the status register content is described in table 7 while an example of the read ? out waveforms is shown in figure 8 and figure 9. the individual status bits are channeled to errn pin with reversed polarity (if a status bit is set, errn is pulled low) at the falling edge on en pin (the status register starts to be shifted only at the second falling edge). as long as the en pin toggling period falls in the den stat range, the operating mode is not changed and the read ? out continues. as soon as the en level is stable for more than dbdmodechange , the read ? out is considered as finished and the operating mode is changed according the current en value. at the same time, the status register bits s4 to s10 are reset provided the particular bits have been read ? out and the corresponding flags are not set any more ? see table 7. the status register read ? out always starts with bit s0 and the exact number of bits shifted to errn during the read ? out is not relevant. table 7. status register bit number status bit content note reset after finished read ? out s0 local wakeup flag reflects directly the corresponding flag no s1 remote wakeup flag s2 not used; always high no s3 power ? on status the status bit is set if the corresponding flag was set previously (the respective high level of the flag is latched in its status counter ? part) yes, if the corresponding flag is reset and the bit was read ? out s4 bus error status s5 thermal shutdown status s6 thermal warning status s7 txen timeout status s8 v bat under ? voltage status s9 v cc under ? voltage status s10 v io under ? voltage status s11 bge feedback normal mode: bge pin logical state (note 3) other modes: low ? s12 ? s15 not used; always low no s16 ? s23 version of the ncv7381 analog part fixed values identifying the production masks version no s24 ? s31 version of the ncv7381 digital part 3. the bge pin state is latched during status register read ? out at rising edge of the en pin. ncv7381 http://onsemi.com 10 receive ? only mode stbn en errn normal mode error flag error flag s0 sx dbdmodechange status register reset den_errn s1 figure 8. example of the status register read ? out (started with en high) den stat_l den stat_h den stat receive ? only mode stbn en errn error flag error flag s0 sx dbdmodechange status register reset den_errn s1 figure 9. example of the status register read ? out (started with en low) den stat_l den stat_h den stat ncv7381 http://onsemi.com 11 table 8. absolute maximum ratings symbol parameter min max units uv bat ? max battery voltage power supply ? 0.3 50 v uv cc ? max 5 v supply voltage ? 0.3 5.5 v uv io ? max supply voltage for v io voltage level adaptation ? 0.3 5.5 v udigin max dc voltage at digital inputs (bge, en, stbn, txd, txen) ? 0.3 5.5 v udigout max dc voltage at digital outputs (errn, rxd, rxen) ? 0.3 v io +0.3 v idigout in ? max digital output pins input current (v io = 0 v) ? 10 +10 ma ubm max dc voltage at pin bm ? 50 50 v ubp max dc voltage at pin bp ? 50 50 v uinh max dc voltage at pin inh ? 0.3 v bat +0.3 v iinh max inh pin maximum load current ? 10 ? ma uwake max dc voltage at wake pin ? 0.3 v bat +0.3 v t j_max junction temperature ? 40 175 c t stg storage temperature range ? 55 150 c uesd iec system hbm on pins bp and bm (as per iec 61000 ? 4 ? 2; 150 pf / 330 ) ? 10 +10 kv uesd ext component hbm on pins bp, bm, v bat and wake (as per eia ? jesd22 ? a114 ? b; 100 pf / 1500 ) ? 6 +6 kv uesd int component hbm on all other pins (as per eia ? jesd22 ? a114 ? b; 100 pf / 1500 ) ? 4 +4 kv uv tran voltage transients, pins bp, bm, vbat and wake. according to iso7637 ? 2, class c (note 4) test pulses 1 ? 100 ? v test pulses 2a ? +75 v test pulses 3a ? 150 ? v test pulses 3b ? +100 v voltage transients, pin vbat. according to iso7637 ? 2 test pulse 5 load dump ? 50 v overvoltage, pin vbat, according to iso16750 ? 2 jump start ? 50 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 4. test is carried out according to setup in flexray physical layer emc measurement specification, version 3.0 . this specification is referring to iso7637. test for higher voltages is planned. table 9. operating ranges symbol parameter min max units uv bat ? op battery voltage power supply 5.5 50 v uv cc ? op supply voltage 5 v 4.75 5.25 v uv io ? op supply voltage for v io voltage level adaptation 2.3 5.25 v uwake op dc voltage at wake pin 0 v bat v udigio op dc voltage at digital pins (en, txd, txen, rxd, rxen, bge, stbn, errn) 0 v io v ubm op dc voltage at pin bm ? 50 50 v ubp op dc voltage at pin bp ? 50 50 v uinh op dc voltage at pin inh 0 v bat v t amb ambient temperature (note 5) ? 40 125 c t j_op junction temperature ? 40 150 c 5. the specified range corresponds to t amb_class1 ncv7381 http://onsemi.com 12 thermal characteristics table 10. package thermal resistance symbol rating value unit r ja_1 thermal resistance junction ? to ? air, jedec 1s0p pcb 78 c/w r ja_2 thermal resistance junction ? to ? air, jedec 2s2p pcb 69 c/w electrical characteristics the characteristics defined in this section are guaranteed within the operating ranges listed in table 9, unless otherwise specified. positive currents flow into the respective pin. table 11. current consumption symbol parameter conditions min typ max unit iv bat ? norm current consumption from v bat normal ? power modes 0.65 1 ma iv bat ? lp low ? power modes; t amb =125 c 75 a sleep mode, v io = v cc = 0 v; t amb = 125 c 80 a low ? power modes, v io = v cc = 0 v, v bat = 12 v, t j < 85 c (note 6) 55 a iv cc ? norm ? idle current consumption from v cc normal mode ? bus signals idle 15 ma iv cc ? norm ? active normal mode ? bus signals data_0/1 r bus = 40 ? 55 37 ma iv cc ? rec receive ? only mode 15 ma iv cc ? lp low ? power modes, t j < 85 c (note 6) 8 a iv io ? norm current consumption from v io normal ? power modes 1 ma iv io ? lp low ? power modes, t j < 85 c (note 6) 6 a itot ? lp total current consumption ? sum from all supply pins low ? power modes; t amb = 125 c 95 a sleep mode, v io = v cc = 5 v, v bat = 12 v, t j < 85 c (note 6) 65 a sleep mode, v io = v cc = 5 v, v bat = 12 v, t j < 25 c (note 6) 55 a 6. values based on design and characterization, not tested in production ncv7381 http://onsemi.com 13 table 12. transmission parameters symbol parameter conditions min typ max unit ubdtx active differential voltage |ubp ? ubm| when sending symbol ?data_0? or ?data_1? r bus = 40 ? 55 ; c bus = 100 pf parameters defined in figure 10. 600 2000 mv ubdtx idle differential voltage |ubp ? ubm| when driving signal ?idle? 0 30 mv dbdtx10 transmitter delay, negative edge test setup as per figure 17 with r bus = 40 ; c bus = 100 pf sum of txd signal rise and fall time (20% ? 80% v io ) of up to 9 ns parameters defined in figure 10. 75 ns dbdtx01 transmitter delay, positive edge 75 ns dbdtxasym transmitter delay mismatch, |dbdtx10 ? dbdtx01| (note 7) 4 ns dbustx10 fall time of the differential bus voltage from 80% to 20% 6 18.75 ns dbustx01 rise time of the differential bus voltage from 20% to 80% 6 18.75 ns dbustxdif differential bus voltage fall and rise time mis- match |dbustx10 ? dbustx01| 3 ns dbdtxia transmitter delay idle ? > active test setup as per figure 17 with r bus = 40 ; c bus = 100 pf parameters defined in figure 11. 75 ns dbdtxai transmitter delay active ? > idle 75 ns dbdtxdm idle ? active transmitter delay mismatch | dbdtxia ? dbdtxai | 50 ns dbustxia transition time idle ? > active 30 ns dbustxai transition time active ? > idle 30 ns dtxen low time span of bus activity 550 650 ns dbdtxactivemax maximum length of transmitter activation 650 2600 s ibp bmshortmax ibm bpshortmax absolute maximum output current when bp shorted to bm ? no time limit r shortcircuit 1 60 ma ibp gndshortmax ibm gndshortmax absolute maximum output current when shor- ted to gnd ? no time limit r shortcircuit 1 60 ma ibp ? 5vshortmax ibm ? 5vshortmax absolute maximum output current when shor- ted to v bat = ? 5 v ? no time limit r shortcircuit 1 60 ma ibp bat27shortmax ibm bat27shortmax absolute maximum output current when shor- ted to v bat = 27 v ? no time limit r shortcircuit 1 60 ma ibp bat48shortmax ibm bat48shortmax absolute maximum output current when shor- ted to v bat = 48 v ? no time limit r shortcircuit 1 72 ma r bdtransmitter bus interface equivalent output impedance (bus driver simulation model parameter) 31 105 500 7. guaranteed for 300 mv and 150 mv level of ubus ncv7381 http://onsemi.com 14 dbdtx10 dbdtx01 dbustx 10 dbustx01 100% 80% 20% 0% utxd 300 mv ? 300 mv ubus 100...4400 ns figure 10. transmission parameters (txen is low and bge is high) ubdtx active ? ubdtx active 100% v io 50% v io 0% v io note: txd signal is constant for 100..4400 ns before the first edge. all parameters values are valid even if the test is performed with opposite polarity. dbdtxia dbdtxai dbustxia dbustxai utxen ? ubdtx ubus figure 11. transmission parameters for transitions between idle and active (txd is low) dtxen low ? 300 mv ? 30 mv 0% v io 50% v io 100% v io ncv7381 http://onsemi.com 15 table 13. reception parameters symbol parameter conditions min typ max unit udata0 receiver threshold for detecting data_0 activity detected previously. |ubp ? ubm| 3 v ? 300 ? 150 mv udata1 receiver threshold for detecting data_1 150 300 mv |udata1| ? |udata0| mismatch of receiver thresholds (ubp+ubm)/2 = 2.5 v ? 30 30 mv udata0_lp low power receiver threshold for detecting data_0 uv bat 7 v ? 400 ? 100 mv ucm common mode voltage range (with respect to gnd) that does not disturb the receiver func- tion and reception level parameters ubp = (ubp+ubm)/2 (note 8) ? 10 15 v ubias bus bias voltage during bus state idle in normal ? power modes r bus = 40 ? 55 ; c bus = 100 pf (note 9) 1800 2500 3200 mv bus bias voltage during bus state idle in low ? power modes ? 200 0 200 mv r cm1 , r cm2 receiver common mode resistance (note 9) 10 40 k c_bp, c_bm input capacitance on bp and bm pin (note 10) f = 5 mhz 20 pf c_bus dif bus differential input capacitance (note 10) f = 5 mhz 5 pf ibp leak ibm leak absolute leakage current when driver is off ubp = ubm = 5 v all other pins = 0 v 25 a ibp leakgnd ibm leakgnd absolute leakage current, in case of loss of gnd ubp = ubm = 0 v all other pins = 16 v 1600 a ubusrx data test signal parameters for reception of data_0 and data_1 symbols test signal and parameters defined in figure 12 and figure 13. rxd pin loaded with 25 pf capacitor. 400 3000 mv dbusrx0 bd 60 4330 ns dbusrx1 bd 60 4330 ns dbusrx10 22.5 ns dbusrx01 22.5 ns dbdrx10 receiver delay, negative edge (note 11) 75 ns dbdrx01 receiver delay, positive edge (note 11) 75 ns dbdrxasym receiver delay mismatch | dbdrx10 ? dbdrx01| (note 11) 5 ns ubusrx test signal parameters for bus activity detection 400 3000 mv dbusactive 590 610 ns dbusidle 590 610 ns dbusrxia 18 22 ns dbusrxai 18 22 ns dbdidledetection bus driver filter ? time for idle detection 50 200 ns dbdactivitydetection bus driver filter ? time for activity detection 100 250 ns dbdrxai bus driver idle reaction time 50 275 ns dbdrxia bus driver activity reaction time 100 325 ns dbdtxrxai idle ? loopdelay 325 ns 8. tested on a receiving bus driver. sending bus driver has a ground offset voltage in the range of [ ? 12.5 v to +12.5 v] and sends a 50/50 pattern. 9. bus driver is connected to gnd and uv cc = 5 v and uv bat 7 v. 10. values based on design and characterization, not tested in production. 11. guaranteed for 300 mv and 150 mv level of ubus. ncv7381 http://onsemi.com 16 table 14. remote wakeup detection parameters symbol parameter conditions min typ max unit dwu 0detect detection time for wakeup data_0 symbol 1 4 s dwu idledetect detection time for wakeup idle/data_1 symbol 1 4 s dwu timeout maximum accepted wakeup pattern duration 48 140 s dwu interrupt acceptance timeout for interruptions (note 12) 0.13 1 s uv bat ? wake minimum supply voltage v bat for remote wakeup events detection ? 5.5 v dbdwakeup reaction remote reaction time after remote wakeup event 7 35 s 12. the minimum value is only guaranteed, when the phase that is interrupted was continuously present for at least 870 ns. table 15. temperature monitoring parameters symbol parameter conditions min typ max unit tjw thermal warning level 125 140 150 c tjsd thermal shut ? down level 150 165 180 c dbdrx10 urxd 300 mv ubus 150 mv dbusrx10 dbusrx01 dbdrx01 figure 12. reception parameters ? 150 mv ? 300 mv ubusrx data ? ubusrx data 100% v io 50% v io 0% v io dbusrx0 bd dbusrx1 bd ncv7381 http://onsemi.com 17 dbdrxia dbusactive urxd ubus dbusrxia dbusidle dbdrxai urxen ? 30 mv dbusrxai figure 13. parameters of bus activity detection ? 150 mv ? 300 mv ? ubusrx 100% v io 50% v io 0% v io 100% v io 50% v io 0% v io table 16. wake pin parameters symbol parameter conditions min typ max unit uv bat ? wake minimum supply voltage v bat for local wakeup events detection 7 v uwake th threshold of wake comparator v bat /2 v dbdwakepulsefilter wake pulse filter time (spike rejection) 1 500 s dbdwakeup reaction local reaction time after local wakeup event 14 50 s iwake pd internal pull ? down current uwake = 0 v for longer than dwakepulsefilter 3 11 a iwake pu internal pull ? up current uwake = v bat for longer than dwakepulsefilter ? 11 ? 3 a table 17. inh pin parameters symbol parameter conditions min typ max unit uinh1 not_sleep voltage on inh pin, when signaling not_sleep iinh = ? 5 ma uv bat > 5.5 v uv bat ? 0.6 uv bat ? 0.27 uv bat ? 0.1 v iinh1 leak leakage current while signaling sleep ? 5 5 a table 18. power supply monitoring parameters symbol parameter conditions min typ max unit ubduvv bat v bat under ? voltage threshold 4 5.5 v ubduvv cc v cc under ? voltage threshold 4 4.5 v uuv io v io under ? voltage threshold 2 2.3 v ubduvv bat ? wake v bat under ? voltage threshold for correct detection of the local wakeup 5 7 v uuv_hyst hysteresis of the under ? voltage detectors 20 100 200 mv ncv7381 http://onsemi.com 18 table 18. power supply monitoring parameters symbol unit max typ min conditions parameter dbduvv cc v cc undervoltage detection time 150 350 750 ms dbduvv io v io undervoltage detection time 150 350 750 ms dbduvv bat v bat undervoltage detection time 350 750 1500 s dbdrv cc v cc undervoltage recovery time 1.5 4.5 ms dbdrv io v io undervoltage recovery time 1 ms dbdrv bat v bat undervoltage recovery time 1 ms table 19. host interface parameters symbol parameter conditions min typ max unit dbdmodechange en and stbn level filtering time for operating mode transition 21 65 s dgo ? to ? sleep go to sleep mode timeout 14 33 s dreactiontime errn reaction time on errn pin error detected 33 s wakeup detected or mode changed 1 s digital input signals table 20. digital input signals voltage thresholds (pins en, stbn, bge, txen) symbol parameter conditions min typ max unit uv dig ? in ? low low level input voltage uv dig = uv io ? 0.3 0.3*v io v uv dig ? in ? high high level input voltage 0.7*v io 5.5 v table 21. en pin parameters symbol parameter conditions min typ max unit r pd _en pull ? down resistance 50 110 200 k ien il low level input current uen = 0 v ? 1 0 1 a den stat en toggling period for status register read ? out 2 20 s den stat_l , den stat_h duration of en low and high level for status register read ? out 1 s den_errn delay from en falling edge to errn showing valid signal during status re- gister read ? out 1 s table 22. stbn pin parameters symbol parameter conditions min typ max unit r pd _stbn pull ? down resistance 50 110 200 k istbn il low level input current ustbn = 0 v ? 1 0 1 a table 23. bge pin parameters symbol parameter conditions min typ max unit r pd _bge pull ? down resistance 200 320 450 k ibge il low level input current ubge = 0 v ? 1 0 1 a ncv7381 http://onsemi.com 19 table 24. txd pin parameters symbol parameter conditions min typ max unit ubdlogic_0 low level input voltage ? 0.3 0.4*v io v ubdlogic_1 high level input voltage 0.6*v io 5.5 v r pd _txd pull ? down resistance 5 11 20 k c_bdtxd input capacitance on txd pin (note 13) f = 5 mhz 10 pf itxd li low level input current utxd = 0 v ? 1 0 1 a 13. values based on design and characterization, not tested in production table 25. txen pin parameters symbol parameter conditions min typ max unit r pu _txen pull ? up resistance 50 110 200 k itxen ih high level input current utxen = v io ? 1 0 1 a itxen leak input leakage current utxen = 5.25 v, v io = 0 v ? 1 0 1 a digital output signals table 26. digital output signals voltage limits (pins rxd, rxen and errn) symbol parameter conditions min typ max unit uv dig ? out ? low low level output voltage irxd ol = 6 ma irxen ol = 5 ma ierrn ol = 0.7 ma (note 14) 0 0.2*v io v uv dig ? out ? high high level output voltage irxd oh = ? 6 ma irxen oh = ? 5 ma ierrn oh = ? 0.7 ma (note 14) 0.8*v io v io v uv dig ? out ? uv output voltage on a digital output when v io in undervoltage r load = 100 k to gnd, either v cc or v bat supplied 500 mv uv dig ? out ? off output voltage on a digital output when unsupplied r load = 100 k to gnd 500 mv 14. uvdig = uvio. no undervoltage on vio and either vcc or vbat supplied. table 27. rxd pin parameters symbol parameter conditions min typ max unit dbdrxd r15 rxd signal rise time (20% ? 80% v io ) rxd pin loaded with 15 pf capacitor (note 15) 6.5 ns dbdrxd f15 rxd signal fall time (20% ? 80% v io ) 6.5 ns dbdrxd r15 + dbdrxd f15 sum of rise and fall time (20% ? 80% v io ) 13 ns |dbdrxd r15 ? dbdrxd f15 | difference of rise and fall time 5 ns dbdrxd r25 rxd signal rise time (20% ? 80% v io ) rxd pin loaded with 25 pf capacitor 8.5 ns dbdrxd f25 rxd signal fall time (20% ? 80% v io ) 8.5 ns dbdrxd r25 + dbdrxd f25 sum of rise and fall time (20% ? 80% v io ) 16.5 ns |dbdrxd r25 ? dbdrxd f25 | difference of rise and fall time 5 ns dbdrxd r25_10 + dbdrxd f25_10 rxd signal sum of rise and fall time at tp4_cc (20% ? 80% v io ) rxd pin loaded with 25 pf capacitor plus 10 pf at the end of a 50 , 1 ns microstripline (note 16) 16.5 ns |dbdrxd r25_10 ? dbdrxd f25_10 | rxd signal difference of rise and fall time at tp4_cc (20% ? 80% v io ) 5 ns 15. values based on design and characterization, not tested in production 16. simulation result. simulation performed within t j_op range, according to flexray electrical physical layer specification, version 3.0.1 ncv7381 http://onsemi.com 20 typical characteristics figure 14. rxd low output characteristic figure 15. rxd high output characteristic irxd ol (ma) ? irxd oh (ma) 30 25 20 15 10 5 0 0 100 200 300 400 500 600 700 30 25 20 15 10 5 0 0 200 400 600 800 1000 1200 figure 16. inh not_sleep output characteristic ? iinh (ma) 5 4 3 2 1 0 0 50 100 150 200 250 300 urxd ol (mv) vio ? urxd oh (mv) vbat ? uinh (mv) temp = 25 c vio = 3.3 v vio = 5 v temp = 25 c vio = 3.3 v vio = 5 v temp = 25 c vbat = 4.9 v vbat = 14 v ncv7381 http://onsemi.com 21 ncv7381 gnd bp bm 100 nf rxd 25 pf figure 17. test setup for dynamic characteristics c bus 10 f 12 v dc v io v cc v bat r bus 5 v dc ncv7381 gnd bp bm 330 pf 100 nf iso 7637 ? 2 pulse generator rxd 15 pf 100 nf figure 18. test setup for measuring the transient immunity 100 nf v io v cc v bat 22 f 22 f 5 v dc 3.3 v dc 330 pf r bus 56 iso 7637 ? 2 pulse generator 22 f ncv7381 http://onsemi.com 22 package dimensions ssop 16 case 565ae ? 01 issue o ncv7381 http://onsemi.com 23 ordering information part number description temperature range package container ? type quantity NCV7381DP0G clamp 30 flexray transceiver ? 40 c to +125 c ssop 16 green tube 76 ncv7381dp0r2g tape & reel 2000 ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. ncv7381/d flexray is a registered trademark of daimler chrysler ag. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative |
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